Sharing idled processor execution resources

ABSTRACT

A processor including a plurality of logical processors, and an instruction set, the instruction set including of one or more instructions which when executed by a first logical processor, cause the first logical processor to make a processor execution resource previously reserved for the first processor available to a second processor in the plurality of processors in response to the first logical processor being scheduled to enter an idle state.

This application is a continuation of U.S. patent application Ser. No.10/772,750, filed Feb. 4, 2004, the content of which is herebyincorporated by reference.

BACKGROUND

In the high level view of a processor depicted in FIG. 1 a, a processormay be conceptualized as being comprised of two components, the firstimplementing the architectural state of the processor, such as forexample its registers and program counter, and the second composed ofprocessor execution resources, such as, for example, a translationlookaside buffer (TLB).

In one type of multiprocessing processor based system, as depicted inFIG. 1 b, multiple physical processors are interconnected by a bussystem, and each physical processor maintains a separate architecturalstate in hardware as well as a separate set of processor executionresources in hardware. In a thread scheduling scenario where eachprocessor of such a system is scheduled to execute a different thread,an instance may arise when one of the processors in the system is idledbecause it is waiting on a slower device in the system, such as a diskdrive, or because it is currently not scheduled to execute a thread. Inthis instance, the processor and all of its execution resources are alsoidled and unavailable to other processors of the system.

In another type of processor based system such as that depicted in FIG.1 c, a hardware processor that maintains separate architectural statesin the processors hardware for a plurality of logical processors may,however, have a single processor core pipeline that is shared by thelogical processors and a single set of processor execution resources,including the TLB, that is shared by the logical processors. Such aprocessor architecture is exemplified by the Intel® Xeon™ processor withHyper Threading Technology, among others, and is well known in the art.

In such a logical multiprocessing system, a thread scheduler mayschedule a different thread to execute on each of the logical processorsbecause each logical processor maintains its architectural stateseparately from all other logical processors. When a logical processoris idled by an operating system thread scheduler or is waiting for datafrom a slow storage device, it may either execute an idle task,typically a tight loop, and periodically check for an interrupt; or itmay suspend its activity and wait for a wake up signal of some type toresume execution of a thread.

In contrast to a multiprocessing system where processor executionresources are physically separated, in this type of logicalmultiprocessing system, when one of the multiple logical processors insuch a system is idled, dynamically allocated processor executionresources that are not being used by the idled logical processor may beavailable to other logical processors that are currently executingthreads for the user or the system.

Processor execution resources in a logical multiprocessing system may,however, be reserved for a logical processor. This may occur indifferent ways. For one example, a logical processor may lock adynamically allocated processor execution resource such as a translationregister (TR) from the TLB thus making it unavailable to other logicalprocessors. In another instance, the logical processor may be staticallyallocated processor execution resources such as TCs and thus thesestatically allocated resources may be unavailable to other logicalprocessors. These reserved resources typically continue to beunavailable to other logical processors even after the logical processorfor which they are reserved is idled. Thus, TRs that are locked by alogical processor generally continue to be locked by the logicalprocessor while it is idling; and statically allocated TCs allocated tothe logical processor continue to be statically allocated to the logicalprocessor while it is idling.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 a-1 c depict high level views of different types of processorarchitectures.

FIG. 2 is a flowchart of processing in one embodiment.

FIG. 3 depicts a processor based system in one embodiment.

DETAILED DESCRIPTION

In one embodiment processing occurs as depicted in the high levelflowchart in FIG. 2. In the figure, two logical processors, Processor 1,200, and Processor 2, 205, are executing threads scheduled by anoperating system that includes a thread scheduler 210. At 215, Processor1 is switched out from an executing thread due to, for instance,termination of the thread or a page fault, and returns to the threadscheduler. If no more tasks are scheduled for this logical processor,220, the processor executes an idling sequence, 225-230. First, thelogical processor gives up any reserved processor execution resourcesheld by the logical processor 225, releasing them to the common pool260. Thus for example, Processor 1 may return a Translation Cache entryor Translation Cache Register to the general pool of registers in theTranslation Lookaside Buffer.

In different embodiments, the processing in step 225 may differ. In someembodiments, the exclusively held resource released may be a dynamicallyallocated resource and have previously been locked by Processor 1. Insuch an embodiment, in step 225, the logical processor unlocks theresource and thereby makes it available to other logical processors. Inanother embodiment, the exclusively held resource may have beenpreviously statically allocated to Processor 1. In such embodiments, instep 225, the statically allocated resource is deallocated and isreturned to the pool of dynamically allocated resources 260.

After Processor 1 enters an idled state, such as a state of suspension230 in this embodiment, it may be requested for execution of a new orresumed thread by a wake up signal such as an interrupt 235. In otherembodiments the processor may enter an idle task loop instead of thesuspension depicted at 230 and periodically check for interrupts.

Following the wake up signal, the logical processor then re-acquires theexclusively reserved resources by either locking or staticallyallocating them to itself as necessary, 240. The logical processor thenswitches to an incoming thread and continues execution of that thread,245.

The resources freed by Processor 1 before suspension or idling at 225become available to another logical processor such as Processor 2, 205,executing a thread such as the depicted user thread 250. These resourcesmay then be dynamically allocated to the logical processor as necessaryfrom the pool of shared processor execution resources during theexecution of the thread, 255.

FIG. 3 depicts a processor based system in one embodiment where thelogical processors are implemented as part of a processor 300. Programsthat execute on the logical processors are stored in memory 340connectively coupled to the processor by bus system 320. The memory mayinclude a non-volatile memory section storing firmware that includes athread scheduler performing processing substantially as described above.

Many other embodiments are possible. For instance, while the abovedescription limits itself to logical processors, similar processing isapplicable to physically separate multiprocessors that share any commonexecution resources. In such embodiments, a hybrid version of logicaland physical multiprocessing is implemented where separate architecturalstates and some execution resources are separated in hardware, but otherexecution resources are shared in hardware and may be released usingprocessing similar to that depicted in FIG. 2. In some embodiments, thethread scheduler referenced above may form a component of firmwareresident in non-volatile memory as depicted in FIG. 3, while in othersit may be a portion of operating system software stored on disk mediaaccessible to the processor. In some embodiments, the actions taken torelease and reserve processor execution resources may be directlyimplemented in hardware and ancillary to the processor's instructionexecution system, while in other embodiments they may be actions takenby the processor as part of the execution of one or more instructions.In some embodiments the shared execution resources may include specialpurpose registers unrelated to the TLB. Embodiments are not limited totwo processors, three or more processors may share execution resourcesand perform processing analogous to the processing described above.

Embodiments in accordance with the claimed subject matter may beprovided as a computer program product that may include amachine-readable medium having stored thereon data which when accessedby a machine may cause the machine to perform a process according to theclaimed subject matter. The machine-readable medium may include, but isnot limited to, floppy diskettes, optical disks, DVD-ROM disks, DVD-RAMdisks, DVD-RW disks, DVD+RW disks, CD-R disks, CD-RW disks, CD-ROMdisks, and magneto-optical disks, ROMs, RAMs, EPROMs, EEPROMs, magnet oroptical cards, flash memory, or other type of media/machine-readablemedium suitable for storing electronic instructions. Moreover,embodiments may also be downloaded as a computer program product,wherein the program may be transferred from a remote computer to arequesting computer by way of data signals embodied in a carrier wave orother propagation medium via a communication link (e.g., a modem ornetwork connection).

Many of the methods are described in their most basic form but steps canbe added to or deleted from any of the methods and information can beadded or subtracted from any of the described messages without departingfrom the basic scope of the claimed subject matter. It will be apparentto those skilled in the art that many further modifications andadaptations can be made. The particular embodiments are not provided tolimit the invention but to illustrate it. The scope of the claimedsubject matter is not to be determined by the specific examples providedabove but only by the claims below.

1. (canceled)
 2. A method comprising: detecting a page fault; switchingout from executing a thread due to the detection of the page fault; andreleasing any resources held by the executing thread.
 3. The method ofclaim 1 including idling the processor executing the thread.
 4. Themethod of claim 2 including determining that the processor is no longeridle and reacquiring the resource.
 5. The method of claim 3 includingcontinuing to execute the thread using the reacquired resource.
 6. Themethod of claim 1 including checking to determine whether anymore tasksare scheduled for the processor executing the thread before switchingout from the executing thread.
 7. The method of claim 6 includingchecking only once before switching out from the executing thread. 8.One or more non-transitory computer readable media storing instructionsexecuted to perform a sequence comprising: detecting a page fault;switching out from executing a thread due to the detection of the pagefault; and releasing any resources held by the executing thread.
 9. Themedia of claim 8, said sequence including idling the processor executingthe thread.
 10. The media of claim 9, said sequence includingdetermining that the processor is no longer idle and reacquiring theresource.
 11. The media of claim 10, said sequence including continuingto execute the thread using the reacquired resource.
 12. The media ofclaim 8, said sequence including checking to determine whether anymoretasks are scheduled for the processor executing the thread beforeswitching out from the executing thread.
 13. The media of claim 12, saidsequence including checking only once before switching out from theexecuting thread.
 14. An apparatus comprising: a processor to detect apage fault, switch out from executing a thread due to the detection ofthe page fault, and release any resources held by the executing thread;and a storage coupled to said processor.
 15. The apparatus of claim 14,said processor to idle.
 16. The apparatus of claim 15, said processor todetermine that the processor is no longer idle and reacquiring theresource.
 17. The apparatus of claim 16, said processor to continue toexecute the thread using the reacquired resource.
 18. The apparatus ofclaim 14, said processor to check to determine whether anymore tasks arescheduled for the processor executing the thread before switching outfrom the executing thread.
 19. The apparatus of claim 18, said processorto check only once before switching out from the executing thread.